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-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/01/2007
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.all;

ENTITY clock_freq_divider IS
	PORT (	clock_in_50MHz : IN  STD_LOGIC;
			clock_out_25MHz: OUT  STD_LOGIC;
			clock_out_12_5MHz: OUT  STD_LOGIC
			);
END clock_freq_divider;

ARCHITECTURE behav OF clock_freq_divider IS
	COMPONENT dflop IS
		PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
				reset			: IN  STD_LOGIC;	-- Resets the flop to 0, active HIGH
				set				: IN  STD_LOGIC;	-- Sets the flop to 1, active HIGH
				input			: IN  STD_LOGIC;	-- Flop input
	      		q	 			: OUT STD_LOGIC 	-- Flop output
				);	
	END COMPONENT;	
	SIGNAL pre_clock_out_25 : STD_LOGIC := '0';
	SIGNAL pre_clock_out_12_5 : STD_LOGIC := '0';
BEGIN
	clock_out_25MHz <= NOT pre_clock_out_25;
	clock_out_12_5MHz <= pre_clock_out_12_5;
	xdflop1: dflop PORT MAP (clock=>clock_in_50MHz, reset=>'0', set=>'0', 
		input=>('1' XOR pre_clock_out_25), q=>pre_clock_out_25);	
	xdflop2: dflop PORT MAP (clock=>clock_in_50MHz, reset=>'0', set=>'0', 
		input=>(pre_clock_out_25 XOR pre_clock_out_12_5), q=>pre_clock_out_12_5);	
	
END behav;



